The EUV Lithography Machine is most responsible for the preparation of chips from 10nm process node to 2nm node, which the leading foundry is using this year to produce its latest chips. As low as the node, a chip feature set that includes transistor. This means that as the process nodes shrink, more transactions can fit within a chip that can make the component more powerful and energy efficient.
EUV lithography machines are important in this regard as they allow circular patterns to hide on silicon waifers with thin lines from human hair. These samples need to be extremely thin so that an application processor (AP) can be properly created to design and adjust billions of transactions. There is only one company in the world that builds an EUV lithography machine and is the Dutch company ASML, which has been banned from sending the machines to China through the United States and the Netherlands where the firm has been headed.
We should tell that Chinese companies, including SMIC, have been able to buy old DUV (deep ultra -violet) lithography machines that can help the manufacture of 7nm chips, which is high where SMIC and Huawei are still trapped. However, there are always rumors about technology that allow China to build an EUV lithography machine.
The latest rumor includes a team from the Shanghai Institute of Optics and Fine Mechanics of the Chinese Academy of Sciences. The team is led by Lin Nan, who worked as the head of Light Source Technology in ASML. Looking for making its EUV Lithography Machine, the group that worked with Lin was able to create an EUV light source platform that is competitive with 13.5-nanomeometer wavelengths used with EUV lithography machines worldwide.
Such progress will mean that Chinese foundrs like SMIC may soon be able to print on circuitry samples on silicon waves, which can find more details with more detail without using a number of samples. The latter is a method in which some foundry EUV lithography is around its disqualification in the source of the machine. This includes breaking the circuit design into simple samples that are hidden in several stages. The problem with this technique is aligning numerous overalls, so when it moves to the waifer, they get it perfectly. There is no tolerance for even a small misunderstanding.
